1. Field of the Invention
This invention relates to a spin-on-glass (SOG) process for improved material properties and performance for very large scale integration (VLSI) interlayer dielectrics by providing for a chemical modification of the SOG materials.
2. Prior Art
As the scale of integration increases and device dimensions decrease, the performance of VLSI chips are limited by interconnection capabilities. For example, VSLI technology for 1-micrometer processes requires a greater control on the materials and techniques that are well beyond that of only slightly larger 2-micrometer processes. While the dimension is scaled in half, the degree of difficulty can increase in the range of 5 to 10 times. Furthermore, as the number of layers of interconnection increases, even more stringent requirements are placed on the interlayer dielectric separating the metal layers.
Multi-layer metallization is required to provide improved interconnection capabilities for increased circuit speed, circuit density, as well as design flexibility for customized applications. However, the surface topography generated by multi-layer processes causes serious difficulties for subsequent processing steps such as lithography, deposition and etching. It also degrades device reliability by causing poor step coverage, metal migration, and stress induced cracking. Therefore, surface planarization is essential for continual progress in integration.
Historically, the interlayer dielectric has been a chemical vapor deposition (CVD) oxide that has produced a less than conformal coating. With decreased metal spacing, this deposition method produces undesirable voids between the tight metal line. The severe topography induced by multi-layer interconnects and conformal coatings increases the difficulties in metal deposition. However, many different approaches have been studied and used to give a more planar dielectric layer, such as, glass flow and reflow, bias sputter quartz, lift-off, etch-back processes and spin-on-dielectric.
Among the several dielectric planarization schemes available, spin-on glass (SOG) offers the greater potential and flexibility as a planarizing medium for the intermetal dielectric. SOG is a smoothing dielectric applied by spin coating that fills the spaces in the smaller geometries. The general composition of SOG materials range from silicates (Si-O) framework to polysiloxanes which contain varying concentrations of methyl and phenyl groups.
Silicates, either undoped or doped, generally solidifies to a rigid film at a rather low temperature and cracks easily for thicker coatings, particularly over surface topography. The polysiloxane materials, with various attach organic groups, were developed to improve the coating characteristics as well as to prevent crack formation for thicker coatings. However, the thickness of polysiloxane films is still limited to approximately 4000 Angstroms (.ANG.).
There are two general process flows employed when SOG is incorporated: etch-back and non-etch-back. For example, U.S. Pat. No. 4,775,550, Chu et al. discloses an etch-back process. In the etch-back process there are less stringent demands placed on the material properties of the SOG since it is surrounded by CVD oxide and does not come in contact with the device. Additional examples of the etch-back process may be found in Prior Art References 2 and 6.
On the other hand, in the non-etch-back process, the SOG is in contact with the device and the material characteristics are extremely important. Several methods of integrating the non-etch-back SOG into the process have been proposed, such as SOG as a stand-alone intermetal dielectric, a CVD dielectric either on top or beneath the SOG to form a dual-film intermetal dielectric, and a sandwich scheme with SOG encapsulated between two layers of CVD dielectric. The simplest technique of SOG planarization would be to use a stand alone SOG film as the intermetal dielectric. However, the current SOG materials cannot spin on 1 micrometer (10,000 .ANG.) thick films and still maintain their crack resistance and dielectric characteristics. As such, the stand alone method is generally considered as an unavailable choice. Increasing the total layer thickness by multiple coats is not effective since extensive cracking is still observed when multiple coatings of SOG are applied.
On the other hand, when thin layers of SOG, in the range of 1000 to 3000 .ANG., are used, a CVD dielectric is needed to form the isolation between the metal layers. As a result of several problems, such as adhesion loss and degradation of film stability, a sandwich scheme with a layer of SOG encapsulated between two layers of CVD dielectric is effective in obtaining planarization without the problems exhibited by a single layer of CVD and a single layer of SOG. A dielectric is the first layer and serves as an adhesion and hillock suppressor layer and should prevent the SOG from coming in contact with the metal. SOG is the second layer and serves primarily as the planarization layer. Finally a CVD dielectric is the third layer and serves as an isolation layer. For a more detailed description of the prior art sandwich processes see Prior Art References 4 and 5.
Theoretically, the SOG layer should transform the severe topography of the device into a smooth one thus allowing the third layer to have a good step coverage and good isolation. However, the SOG materials generally used have problems associated with it. The thickness at which the SOG materials crack is dependent on the chemical composition. In general, the silicate material will exhibit cracking when coating thicknesses exceed 1000 .ANG., whereas the polysiloxanes are more crack resistant and can be coated to approximately 3000 to 4000 .ANG.. However, SOG films exceeding thickness of 3000-4000 .ANG. over severe surface topography exhibit extensive and severe cracking.
As a result of the a thick film's tendency to crack, the planarity of a single thin SOG spin application is generally not adequate, therefore at least two or more coats applied in sequence are necessary to obtain satisfactory planarity. For an example of multi-layer processes see Prior Art Reference 3. Although there is a need to be able to coat the devices with film thicknesses of 4000 to 7000 .ANG., the desired film thickness by using multiple layers of thin coats can not be obtained above approximately 4500 .ANG. without an extensive and severe cracking problem. Additionally, the application of multiple layers decreases the ease of production, therefore correspondingly increases production costs.
Another problem typically associated with SOG materials is their susceptibility to dilute HF etching baths and to oxygen plasma. Deposited silicon and aluminum layers are very readily oxidized and a "native oxide" is created on the surface. Before proceeding with the next step in the process, the native oxide must be removed to obtain a clean surface. The native oxide is typically removed by dipping the wafer in an etching bath. However, the SOG material is strenuously attacked by the etching bath, resulting in a severe loss of the SOG layer. Additionally, problems arise with the metal deposition in the vias of the device.
Another disadvantage of the SOG material is their sensitivity to oxygen plasma. Generally, the oxygen plasma reacts with the organic groups of the film replacing them with hydroxyl groups (--OH). This reduces the etch resistance and inhibits the ability to dip the devices in etching solution. Generally, the limitation of the SOG material is solved by changing the process flow to avoid these sensitivity problems.
The SOG layer may also be used to reduce the surface topography before the deposition of the final passivation layer. For example, the final passivation layer for a 1.5 .mu.m CMOS process consisted of a one micrometer thick oxynitride layer capped with a two micrometer thick phosphorus doped glass layer. The process using a passivation layer proved to be adequate until the device dimensions were reduced to one micrometer or less. Because of the severe topography of the scaled down devices, the CVD oxynitride layer tended to develop defects or microcracks in the narrow spacing due to severe shadowing and stress effects. Theoretically, the problems can be reduced or eliminated when an SOG layer is used to reduce the surface topography. With a thin layer of SOG, 2000 .ANG., the topography is still quite severe. Although, a 4000 .ANG. layer appears to be adequate, the problems associated with the thicker SOG layers are now prevalent and prohibit the use of 7000 .ANG., which would be a most desirable thickness.